Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic - VLSI Project

Current electronic systems which primarily consist of embedded circuitry focus on high-end application streams. It is prescribed for the productive utilization of computationally demanding digital signal processing (DSP) functions. For the digital signal processing (DSP) stream, hardware stimulation has been tested as an excessively auspicious implementation technique. The fusion of heterogeneity through functional hardware stimulators upgrades performance and decreases energy expenditure. 

As the multiple instantiated application-specific integrated circuits (ASICs) are required to quicken several kernels, ASIC creates the optimal accelerator solution in charge of overall power and design performance and their obstinacy to expand silicon complexity. In the initial data-flow graph (DFG) of the kernels, soaring performance formative data paths have been visualized to precisely map primitive or linked operations. 

In a controlled evident template library, the templates of convoluted linked operations are either derived precisely from the kernel’s data flow graph. Design selections on the stimulator datapath hugely bump its efficiency. The utilization of architecture level expansions like enlarged instruction-level replicas has worked on obscene grained decomposable datapaths.

For obtaining a tailored design structure, the domain explicit architecture formation algorithms alter the type and number of estimation units. Handling of multiple ALUs with heterogeneous arithmetic appearances has adopted an intrusive operation which is the string to set up the computation of integrated subexpressions.

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At the enclosed circuit design of primitive factors like adders throughout the logic, synthesis has kept forward reformable architectures which ruled out the arithmetic expansion throughout the arithmetic synthesis. The research studies have indicated that the arithmetic expansion at higher abstraction stages than the structural design. It has a symbolic impact on the datapath enforcement.

At the post, RTL design level, timing induced expansion depends on carry-save (CS) arithmetic. For optimizing linear DSP circuits, the common subexpression process which is utilized to cancel out the CS stage. The main drawback of this process is that the CS expansion has fringed to combined addition and subtraction operations only.

The conversion between CS and binary stage has been interpolated before every operation that is distinct from addition or subtraction operations like multiplication function. Due to time engrossing carry propagation, the apportioned multiple CS to binary conversions that hugely reduces design performance.

Procedure: Due to the essential benefit of cancelling the large carry generation links, the carry saves (CS) process has been extensively utilized to map fast arithmetic circuitry. The main target is to exaggerate the grade that a CS computation is executed within the DFG.

The derived flexible accelerator process can be formulated as –

W*=A×X*+Y*+K*………………………………………… (1)

W*=A×K*+X*+Y* …………………………………………. (2)

Where it holds the important CS stage relationship, which is given as –

X*=XC,XS=XC+XS ………………………………………….. (3)

There are two multiplexers (MUX1 and MUX2) available and the input carry signal is represented as –

N*=X*-Y* ……………………………………………………….. (4)

This term (X*-Y*) is valid for CL0 =1. The more values of clock signals can also be found.

Conclusion: For implementing the fast linking of additive and multiplication operations, the formative accelerator design has been recommended that manipulates the fusion of CS arithmetic expansions. The result has been shown that this improves 61.91% in area-delay products and 54.43% in energy consumption compared to the classical method.

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• VLSI
• Digital Signal Processing

• VLSI Design
• DSP

Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic