Fully Reused VLSI Architecture of Fm0/Manchester Encoding Using Sols Technique for DSRC Applications

Overview- In the modern age of secured communication, the dedicated short-range communication (DSRC) is rising technology to launch the inventive transportation system and typically DSRC standards endorse the FM0 and Manchester codes to attain dc-balance and raising the signal reliability. For designing the restated VLSI architecture for FM0 and Manchester codes, the coding diversity has restricted the utility which established the correlation between both coding techniques.

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A protocol which provides the one way or two-way medium spectral communication exclusively for inventive transportation systems are referred to as DSRC and it can be divided into two divisions-

1. Automobile to automobile: The DSRC permits the message sending and transmitting among automobiles for safety problems includes blind spot, intersection cautioning, inter cars distance and collision unease. 
2. Automobile to roadside: It centralized on the inventive transportation duties like electronic toll collection (ETC) system. The toll compilation is electrically proficient with the contactless IC card dais by ETC and it can be drawn out to the wages for parking facilities and gas resumptions.

According to DSRC standards, the data rate independently marks at 500 kb/s, 4 Mb/s and 27Mb/s with carrier frequency range from 5.8 to 5.95 GHz and utilized modulation techniques are amplitude shift keying (ASK), phase-shift keying (PSK), orthogonal frequency division multiplexing (OFDM). The waveform of the broadcasting signal is expected to contain zero mean for robustness problem and it is called a dc balance. 

The problematic conditions occur to obtain the dc balance due to the transmitted signal abides of arbitrary binary progression. The determination of FM0 and Manchester codes can grant the broadcasted signal with dc balance.

Procedure- As we talk about the coding principles of both codes, the clock signal and the input data are denoted as CLK and X. The encoding methods can be divided into 2 types-

1. FM0 Encoding: The FM0 code lies of two parts for each X, which is given as below.First one for the former half-cycle and the second one for the later half cycle. The thumb rules for this method is given as follows-

1. If X is logic 0, so FM0 code must flaunt the transition between A and B.
2. If X is logic 1, a transition is not conceded between A and B.
3. The transaction is allotted among every FM0 code irrespective of the value of X.

The boolean equations of A(t) and B(t) are given as

At=B(t-1) ……………………………………… (1)

Bt=X±B(t-1) ………………………………… (2)

From both A(t) and B(t), the boolean expression of FM0 is denoted as

Ft=CLK At+CLK B(t) ……………………….. (3)

• Manchester Encoding: The Manchester coding is denoted as

Ft=X±CLK ………………………………. (4)

It can be executed with an XOR operation for CLK and X.

Conclusion- The reason for the restriction on hardware usage of VLSI architecture design is that the coding divergence between FM0 and Manchester encoding. The SOLS technique wiped out the restriction on hardware usage by two distinct techniques, first one is area compact retiming and balances logic function sharing. The reduction of hardware resources up to 22 transistors can possible through area compact retiming method. 

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Fully Reused VLSI Architecture of Fm0/Manchester Encoding Using Sols Technique for DSRC Applications