Latest Projects Based on Vlsi Design

Traffic lights help people to move properly in the junctions by stopping the route for one side and allowing the other. But most of the traffic lights have fixed time controller which makes the vehicles to stop for a long time during peak hours. Because of this, traffic congestion is increased during peak hours. Sometimes traffic police placed in the congestion areas to manage the traffic this shows the ineffectiveness of the system. While for smaller roads sensors are used to control the traffic autonomously.

In this VLSI design project, we will design an FPGA based traffic light controller system which reduces the waiting time of the drivers during peak hours. VHDL is used to design FPGA because with VHDL you can simulate the operation of digital circuits from an easy one to complex gates.

Nowadays, accidents in highways are increased due to the increase in the number of vehicles. To avoid collisions between vehicles the speed of the vehicle is reduced or the driver is alerted when it nears the preceding vehicle. In this VLSI design project, we will design a PID controller based on fuzzy logic using Very Highspeed Integration Circuit Hardware language for automobile’s cruising system. 

Nowadays, robots are used for various applications. From home to big industries robots are implemented to perform repetitive and difficult jobs. Robots are preferred over human workers because robots are machines which can able to work 24x7 without getting tired. Because of its wide range of applications some industries use multiple robots in the same place. In such a case, there might be a chance of collision between robots. To solve this problem we are going to propose a solution using RFID tags.

In this VLSI design project, we are going to develop an anti-collision robot processor which is combined with a smart algorithm to avoid crashes with other robots and physical objects using RFID. The algorithm is implemented in VHDL (VHSIC - HDL Very Highspeed Integrated Circuit - Hardware Description Language) and simulated using Xilinx simulation software.

Error Correction Codes (ECCs) recommends a delayed penalty in pervading the data as encoding or decoding has to be executed. ECCs are extensively used to conserve memory and to bypass data corruption. Due to hindering the use of ECCs in high-speed memories, it led to the use of Single Error Correction Double Error Detection (SECDED) codes. 

Multiple Cell Upsets (MCUs) becomes more familiar and restrict the use of SEC-DED codes unless they are joined with interleaving as technology scaled up. The biggest issue in memories is arising the errors which can be explained i.e. by radiation-induced soft errors that alter one or more memory cells, shift their values and other deficiencies cause permanent damage. 

Overview

Redundant basis (RB) multipliers over Galois Field (GF(2m)) have obtained tremendous popularities in elliptic curve cryptography (ECC) primarily because of their imperceptible hardware cost for squaring and modular devaluation. Multiply operations over a fixed field can be utilized to execute other operations i.e. division, exponentiation and inversion. Multiplication over Galois field can be enforced on a general-purpose machine but it is excessive to use GP machine to resolve cryptographic systems in cost-conscious products.

The need for hardware utilization of fixed range computation functions for the advantages like low cost and high throughput rate for the uttermost real-time applications. The prime of basis to exhibit field parameters namely the polynomial basis, normal basis, triangular basis and redundant basis (RB) has a dominant impact on the achievement of the arithmetic circuits and offer free squaring.

Overview- In the modern age of secured communication, the dedicated short-range communication (DSRC) is rising technology to launch the inventive transportation system and typically DSRC standards endorse the FM0 and Manchester codes to attain dc-balance and raising the signal reliability. For designing the restated VLSI architecture for FM0 and Manchester codes, the coding diversity has restricted the utility which established the correlation between both coding techniques.

ABSTRACT

This VLSI project shows the design, building and testing of an FM receiver. This system is divided into two parts the analogue FM modulator and digital demodulator. The main part of this work is to convert the RF signal into a frequency lower than the sample to a digital converter. The second part works as a phase loop method of demodulating FM signal.

In this VLSI project, we will discuss how an algorithm lock and track the objects. This algorithm is created to use the highly similar building and the speed of VLSI implementation of the cellular neural network universal machine. The algorithm has the ability to lock on the object and analyze the coordinates within the image. CNN chip-specific robust templates are produced in order to implement the method on a real CNN-UM chip. The tests and results of the study show that a CNN-UM chip which runs this procedure can be used in real-time tracking application which able to achieve good performance. In upcoming days the object tracking system becomes more important in use.

Current electronic systems which primarily consist of embedded circuitry focus on high-end application streams. It is prescribed for the productive utilization of computationally demanding digital signal processing (DSP) functions. For the digital signal processing (DSP) stream, hardware stimulation has been tested as an excessively auspicious implementation technique. The fusion of heterogeneity through functional hardware stimulators upgrades performance and decreases energy expenditure. 

As the multiple instantiated application-specific integrated circuits (ASICs) are required to quicken several kernels, ASIC creates the optimal accelerator solution in charge of overall power and design performance and their obstinacy to expand silicon complexity. In the initial data-flow graph (DFG) of the kernels, soaring performance formative data paths have been visualized to precisely map primitive or linked operations. 

In a controlled evident template library, the templates of convoluted linked operations are either derived precisely from the kernel’s data flow graph. Design selections on the stimulator datapath hugely bump its efficiency. The utilization of architecture level expansions like enlarged instruction-level replicas has worked on obscene grained decomposable datapaths.

For obtaining a tailored design structure, the domain explicit architecture formation algorithms alter the type and number of estimation units. Handling of multiple ALUs with heterogeneous arithmetic appearances has adopted an intrusive operation which is the string to set up the computation of integrated subexpressions.

Overview: In any digital signal processing, image and video processing, wireless communication and biomedical signal processing systems, the Finite Impulse Response (FIR) filter contains broad ranges of applications like Software Defined Radio (SDR) and manifold classic video codecs. A sanctioned finite impulse response (FIR) filter with emphatically acquirable filter coefficients, installation factors and spaces which may alter according to the stipulation of distinct standards in a compact computing scheme to verify it.

A powerful reformable FIR filter with momentous changes can trigger the system inventor to evolve the chip with minimal cost, power and area as well as the proficiency to engage at ultra-high speed. The multiplier is the leading constraint in any finite impulse response (FIR) filter which describes the enforcement of the aimed filter.

In materializing cryptographic systems, fixed field multipliers including huge throughput rank and least latency have attained enormous attention. According to National Institute Standard Technology (NIST) standards, the polynomials are not sufficient over GF (2m) in such multipliers. It utilizes elliptical curve cryptography (ECC) to execute direct additions and direct magnifying operations on an elliptical curve where fixed field multiplication upon GF (2m) is a normal field operation.

If an individual processing element (PE) has the identical circuit layout and one PE can cut the signals to its bordering PE at an immense speed on an entirely pipelined route, the systolic designs hand over area-time productive exertion due to modularity and consistency of their structures. It is dependent on exclusive polynomials where scientist Meher has represented productive bit-parallel systolic design for multiplication upon GF (2m). 

Digit serial multipliers dependent on polynomials are registered to attain area time resolution. Typically, all extending systolic multipliers as well as the bit-parallel and digit serial designs, having huge latency and deteriorate from definite more things as described below –

1. The structures which definitely contain giant resistor intricacy not alone for pipelining, but also for giving the wobbled intake to processing element to delay for the disburse acquired sectioned products are called as bit-parallel systolic structures.
2. The conditions applied on the structures which certainly expands with digit intensity or field regulation and it decreases throughput volume quite efficiently are the critical route of digit serial systolic designs.
3. Digit serial designs expand with digit intensity or field regulation irrespective of the impact of average computational time (ACT).

Overview: The filter characterization which brings a straightforward and impressive path to verify that an element exists to a set is called as Bloom filters. The application areas of these special filters can be a networking field and computer architectural design units. It is also utilized in huge databases like Google Bigtable utilizes it to decrease the disk scans. 

The classical structure of Bloom filters has been prolonged over the period of time like counting BFs have popularized to allow the elimination of elements from BFs. The derived compressed bloom filters (CBFs) has been recommended for advancing the transmission among the network. Freshly, the bloom filter codes have been scheduled for executing the error correction in huge data sets.

Bloom filters (BFs) can be enforced with the use of electronic devices in main cases. In tremendous memory cells, the recorded blocks of BFs can be reserved and the necessary processing is complete in the processor or in a devoted system. In a minimal speed memory cells, the required sets which are using to form the BFs have saved.

Nonetheless, the technology extents, the reliability of the electronic circuits has drastically decreased and created severe problems to implement it. Due to the technology scaling, error appearance by internal radiations, inferences and other holdings are becoming very normal. Then, the moderation techniques are utilized at distinct stages to confirm that the required circuitry is approaching reliability in quick succession. Memories are the demanding parameter for Bloom filters (BFs) exertion.

In the modern era of integrated circuit (IC) technology, multicore chip architectures need no insignificant test results introduced by the ruthless diminish of semiconductor devices which work as much faster and lower power consumption than ancient predecessors. This progression has inclined upwards to the spreading demand of SoC designs over their capability to enclose several diverse kinds of convoluted IP cores proceeding at distinct clock rates with distinctive power stimulations and numerous power-supply voltage stages.

It is obliged to cover test access mechanisms (TAM) and test capsules for several SoC dependent test patterns derived to employ devoted instruments. Test access mechanisms (TAMs) are generally used for the relocation of experimental data between the structure on-chip cores and embedded cores. As soon as the functions of upgrade test interface design or control logic, the results of both TAMs and test wrappers have been completed while consigning routing and layout restraints or grouping of cores.

Overview: Microelectronics processor can execute various operations but the most prioritised operation is binary addition. For implementing digital logic in synchronous circuitry, several types of adders have been formed that even correspond to the vigorous interest in asynchronous or clockless circuits. There are no needs for time quantization processes in asynchronous circuits.

As logic designs are independent of various issues of synchronous or clocked circuits, they provide huge capability under it. Through a request-acknowledgement handshaking protocol, logic design charts in asynchronous circuits are restrained to develop a pipeline mechanism in the hooky of clocks. As long as the bit adders are extravagant, it is useful for minor elements in definite handshaking blocks.

Latest Projects based on vlsi design